Field of the Invention
The present invention relates to a method for storing register properties of a hardware device having a heterogeneous memory in a datastructure as described in the preamble of claim 1 and a data structure for holding register properties of a hardware device having a heterogeneous memory as described in the preamble of claim 2.
Such a method and data-structure already are known in the art in test-systems including a test device for executing access tests on Application specific integrated circuits, further referred to as ASICs, that are mounted on a Printed Circuit Board and coupled to a micro-processor. Such a system is called an embedded hardware application. These, before mentioned, access tests consist of tests on the interconnections between a host microprocessor and its peripheral devices such as ASICs in this so-called embedded hardware application.
In such embedded hardware applications, ASICs and RAMs are mapped to a given address range, i.e. the processor can access them through memory access in the given address range. In other words, they are memory mapped.
ASICs typically have a heterogeneous memory-map as opposite to the homogenous memory map of RAM. With RAMs, all address in the given range are mapped to a different storage location in the RAM, each storage location has the same amounts of accessible bits and all of them have the same property (e.g. all bits are read/writable).
ASICs, on the other hand, have addresses in the given range that are not mapped to a register in the ASIC. (A storage location in the ASIC is typically called a register.) These are the so-called memory holes, wherein any access to those holes typically leads to unpredictable results. Furthermore, ASICs registers often differ in width from one address location to the other. The initial value (value after reset) of ASICs registers can vary from one address to the other.
Finally, ASICs registers do have different properties. These register properties are defined by the property of each bit in the register. At bit-level following properties are defined, a register may consist out of a mixture of these bit properties:                read writable bits where the processor can set the value, and read its setting, the read only bits wherein the processor can only read its setting, and can't change it and at last the read-reset bit where the hardware clears this bit after any read access of the processor.        
To be able to apply an algorithm, such as an access test e.g. in a test system, that makes abstraction from the properties of an ASIC, one needs a data-structure holding the properties of that ASIC. Currently this is performed in a huge array. For each address of the ASICs address range, an entry is foreseen in this array. Each entry holds the properties of the register at the given address.
In such a test-system a data structure is used wherein each address in the range of the ASIC's memory space, is mapped to an entry in an array of register properties. In that way, the device properties of a device are represented by the array, i.e. the memory map.
Device properties of an ASIC to be tested are stored in a memory map. The storage of these device properties in the arrays of the memory map, requires a large memory space as all data is stored sequentially for each address of the ASIC, to be tested. Moreover, this memory map of a device is often unstructured with specific register properties and besides containing unused addresses.
Hence, it is disadvantageous that a large memory storage space is required to store all device properties due to the structure of such a memory map and moreover it is even more disadvantageous because due to the format and the distribution of the device properties necessary the retrieval-time of the data is substantially large.